Integrated circuits have gained extensive use over the last two decades and have been incorporated into a substantial number of electronic devices. At the same time, however, the size of these integrated circuits have continuously shrunk in size to accommodate ever faster and smaller electronic devices. The varied application of the electronic devices into which integrated circuits have been placed has required different types of process modules. Thus, integrated circuit manufacturers responded by developing the capability to produce different types of these modules. In many cases, they devoted entire lines within a plant to the task of producing a particular process module. As customers' expectations of electronic devices have increased, manufacturers found that it was necessary to incorporate several different modules into one device, and in some cases, even into one chip.
The incorporation of these process modules, such as dense memory, FLASH devices, bipolar devices and analog components along with the core digital CMOS technologies is presently a daunting task. In the past, these enhancement modules have often incorporated processes that were significantly different than that required by the core digital process. In particular, enhancement modules typically use 3.3 volt technology while core digital circuits employ 2.5 volt technology. Also, circuits often required different combinations of these enhancement modules. This requirement has in the past meant that manufacturers have needed to develop, maintain and qualify numerous technologies to support the varied customer and product requirements.
Traditionally, the integration of various system-level components, such as precision analog functions, cache memory, and small-signal radio frequency (RF) with core logic has required the use of separate and mutually incompatible fabrication processes implemented as separate chips at the board level. Attempting to integrate RF and analog functions with digital functions on a single chip has not been possible in process technologies of 0.35 micron, or even 0.5 micron, because the processes associated with RF devices, such as bipolar or BiCMOS, have not been easily adaptable to the needs of digital components, and CMOS processes have not been capable of handling the high-frequency requirements of RF devices.
Separate chips with separate fabrication processes not only result in increased cost and time-to-market, but also place a significant burden on wafer fabrication plants to qualify and maintain multiple process technology lines--one for each of these unique components.
Another way in which manufacturers have attempted to address this problem has been to build the module around a single technology, such as a 3.3 volt technology and then to insert circuitry to accommodate a lower voltage device, such as a 2.5 volt CMOS technology. This type of design is typically built using a 0.33 micron gate with a thick gate oxide. While this type of configuration has allowed for both types of devices to operate on a single platform, the operation of the 2.5 volt device on the 3.3 volt platform has been found to have its own inherent disadvantages. For example, a transistor that is optimized for 3.3 volts but is operated at 2.5 volts will have lower drive current than a transistor that is optimized for 2.5 volts.
Accordingly, what is needed in the art is a process that economically and efficiently incorporates both 2.5 volt and 3.3 volt technologies into a single microchip.